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Advance Program:

Nov. 23, 2009

9:00-12:00 Tutorial 1
Power-Aware Testing and Test Strategies for Low Power Devices

13:30-16:30 Tutorial 2
System-in-Package Test Strategies

Nov. 24, 2009

9:00-10:30 Plenary Session 1

9:00-9:20 Opening Remarks

9:20-9:55 Keynote Speech 1
Testing Challenges for Emerging Nanotechnologies
Niraj K. JHA (Princeton University, USA)

9:55-10:30 Keynote Speech 2
Wireless Testing and 3D Integrated Devices: Can They Save Our Jobs?
Cheng-Wen WU (Industrial Technology Research Institute, Taiwan)

10:50-12:00 Plenary Session 2

10:50-11:25 Keynote Speech 3
Can innovations in Test serve as a beacon of light in a dark economy?
Sanjiv TANEJA (Cadence Design Systems, USA)

11:25-12:00 Keynote Speech 4
Challenges and Solutions for Testing TSV-Based 3D-SICs
Erik Jan MARINISSEN (IMEC, Belgium)

13:10-14:30 Session 3A: BIST

CA Based Built-In Self-Test Structure For SoC
Sukanta DAS, Biplab K SIKDAR (Bengal Engineering and Science University, Shibpur - India)

A Random Jitter RMS Estimation Technique for BIST Applications
Jae Wook LEE, Ji Hwan CHUN, Jacob ABRAHAM (The University of Texas at Austin - USA)

A Novel Seed Selection Algorithm for Test Time Reduction in BIST
Rupsa CHAKRABORTY, Dipanwita ROY CHOWDHURY (IIT, Kharagpur - India)

Logic BIST Architecture for System-Level Test and Diagnosis
Jun QIAN (Cisco Systems, Inc. - USA), Xingang WANG, Qinfu YANG, Fei ZHUANG, Junbo JIA, Xiangfeng LI, Yuan ZUO, Jayanth MEKKOTH, Jinsong LIU (SynTest Technologies, Inc. - China), Hao-Jan CHAO (SynTest Technologies, Inc. - Taiwan), Shianling WU, Huafeng YANG, Lizhen YU, FeiFei ZHAO, Laung-Terng WANG (SynTest Technologies, Inc. - USA)

13:10-14:30 Session 3B: Fault Diagnosis

Fault Diagnosis under Transparent-Scan
Irith POMERANZ (Purdue University - USA), Sudhakar REDDY (University of Iowa - USA)

Scan Chain Diagnosis by Adaptive Signal Profiling with Manufacturing ATPG Patterns
Yu HUANG, Wu-Tung CHENG, Ruifeng GUO, Ting-Pu TAI (Mentor Graphics Corporation - USA), Feng-Ming KUO, Yuan-Shih CHEN (Taiwan Semiconductor Manufacturing Company - Taiwan)

On Improving Diagnostic Test Generation for Scan Chain Failures
Xun TANG (University of Iowa - USA), Ruifeng GUO, Wu-Tung CHENG (Mentor Graphics Corporation – USA), Sudhakar REDDY (University of Iowa - USA), Yu HUANG (Mentor Graphics Corporation – USA)

On Scan Chain Diagnosis for Intermittent Faults
Dan ADOLFSSON (NXP Semiconductors - Netherlands), Joanna SIEW (Philips Applied Technologies - Netherlands), Erik Jan MARINISSEN (IMEC - Belgium), Erik LARSSON (Linköpings Universitet - Sweden)

13:10-14:30 Session 3C: Analog and Mixed-signal Testing

Design-for-Test Circuit for the Reduced Code Based Linearity Test Method in Pipelined ADCs with Digital Error Correction Technique
Jin-Fu LIN, Soon-Jyh CHANG (National Cheng-Kung University - Taiwan)

Multi-Tone Testing of Linear and Nonlinear Analog Circuits using Polynomial Coefficients
Suraj SINDIA, Virendra SINGH (Indian Institute of Science - India), Vishwani AGRAWAL (Auburn University - USA)

Low Cost Dynamic Test Methodology for High Precision Σ∆ ADCs
S. KOOK, H. CHOI, V. NATARAJAN, A. CHATTERJEE (Georgia Tech – USA), A. GOMES, S. GOYAL, L. JIN (National Semiconductor Corporation – USA)

Very-Low-Voltage Testing of Amorphous Silicon TFT Circuits
Shiue-Tsung SHEN, Wei-Hsiao LIU, En-Hua MA, James Chien-Mo LI, I-Chun CHENG (National Taiwan University - Taiwan)

14:45-16:05 Session 4A: Industrial Session

Scan Compression Implementation in Industrial Design - Case Study
Dragon HSU (Ralink), Ron PRESS (Mentor Graphics Corp. - USA)

Calibration as a functional test: An ADC case study
Hsiu-Ming (Sherman) CHANG (ITRI), Kuan-Yu LIN, Kwang-Ting (Tim) CHENG

Customized Algorithms for High Performance Memory Test in Advanced Technology Node
Shomo CHEN  (Trident), Ning HUANG, Ting-Pu TAI, Actel NIU

A Practical DFT Approach for Complex Low Power Designs
Augusli KIFLI (Faraday), Y.W. CHEN, Y.W. TSAY, K.C. WU

DFT Challenges in Next Generation Multi-media IP
Vishwanath S, Mukund MITTAL (TI), Subrangshu DAS

Yield Ramp up by Scan Chain Diagnosis
Feng-Ming KUO (TSMC), Yuan-Shih CHEN (Taiwan Semiconductor Manufacturing Company - Taiwan)

14:45-16:05 Session 4B: Low-Power Testing

CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing
Kazunari ENOKIMOTO, Xiaoqing WEN, Yuta YAMATO, Kohei MIYASE (Kyushu Institute of Technology - Japan), Hiroaki SONE (Fukuoka Industry, Science & Technology Foundation - Japan), Seiji KAJIHARA (Kyushu Institute of Technology - Japan), Masao ASO, Hiroshi FURUKAWA (NEC Micro Systems - Japan)

New Scheme of Reducing Shift and Capture Power Using the X-Filling Methodology
Jiann-Chyi RAU, Tsung-Tang CHEN, Wei-Lin LI, Po-Han WU (Tamkang University - Taiwan)

Deterministic Built-in Self-Test Using Multiple Linear Feedback Shift Registers for Low-Power Scan Testing
Lung-Jen LEE, Wang-Dauh TSENG, Rung-Bin LIN, Chi-Wei YU (Yuan Ze University - Taiwan)

14:45-16:05 Session 4C: On-Line Testing and Silicon Debug

Low Overhead Time-Multiplexed Online Checking: A Case Study of an H.264 Decoder
Ming GAO, Kwang-Ting CHENG (University of California, Santa Barbara - USA)

A FPGA-based Reconfigurable Software Architecture for Highly Dependable Systems
Alberto SCIONTI, Stefano DI CARLO, Paolo PRINETTO (Politecnico di Torino - Italy)

Using Non-Trivial Logic Implications for Trace Buffer-based Silicon Debug
Sandesh PRABHAKAR, Michael HSIAO (Virginia Tech - USA)

A Post-silicon Debug Support Using High-level Design Description
Yeonbok LEE, Tasuku NISHIHARA, Takeshi MATSUMOTO, Masahiro FUJITA (The University of Tokyo - Japan)

16:20-17:40 Session 5A: Delay Testing

A Low Overhead On-chip Path Delay Measurement Circuit
Songwei PEI, Huawei LI, Xiaowei LI (Chinese Academy of Sciences - China)

An Adaptive Test for Parametric Faults Based on Statistical Timing Information
Michihiro SHINTANI, Kazumi HATAYAMA (Semiconductor Technology Academic Research Center - Japan), Takashi SATO (Kyoto University - Japan), Takumi UEZONO (Tokyo Institute of Technology - Japan)

A Delay Measurement Technique Using Signature Registers
Kentaroh KATOH, Toru TANABE, Haque ZAHIDUL, Kazuteru NAMBA, Hideo ITO (Chiba University - Japan)

Functional Built-in Delay Binning and Calibration Mechanism for on-Chip at-Speed Self Test
Chen-I CHUNG, Jyun-Sian JHOU, Ching-Hwa CHENG, Sih-Yan LI (Feng-Chia University - Taiwan)

16:20-17:40 Session 5B: Test Generation (I)

A Practical Approach to Threshold Test Generation for Error Tolerant Circuits
Hideyuki ICHIHARA, Kenta SUTOH, Yuki YOSHIKAWA, Tomoo INOUE (Hiroshima City University - Japan)

Speeding up SAT-based ATPG using Dynamic Clause Activation
Stephan EGGERSGLUESS, Daniel TILLE, Rolf DRECHSLER (University of Bremen - Germany)

N-distinguishing Tests for Enhanced Defect Diagnosis
Gang CHEN, Janusz RAJSKI (University of Iowa - USA), Sudhakar REDDY (University of Iowa - USA), Irith POMERANZ (Purdue University - USA)

Dynamic Compaction in SAT-Based ATPG
Alejandro CZUTRO, Ilia POLIAN, Piet ENGELKE (Albert-Ludwigs-University - Germany), Sudhakar REDDY (University of Iowa - USA), Bernd BECKER (Albert-Ludwigs-University - Germany)

16:20-17:40 Session 5C: System Test

SIRUP: Switch Insertion in RedUndant Pipeline Structures for Yield and Yield/Area Improvement
Mohammad MIRZA-AGHATABAR, Melvin BREUER, Sandeep GUPTA (University of Southern California - USA)

Transaction Level Modeling and Design Space Exploration for SOC Test Architectures
Chin-Yao CHANG, Chih-Yuan HSIAO, Kuen-Jong LEE (National Cheng Kung University - Taiwan), Alan SU (Global Unichip - Taiwan)

Efficient Software-based Self-test Methods for Embedded Digital Signal Processors
Jun-Jie ZHU, Wen-Ching LIN, Jheng-Hao YE, Ming-Der SHIEH (National Cheng Kung University - Taiwan)

Nov. 25, 2009

9:00-10:20 Session 6A: Panel Session (I):
Is Low Power Testing Necessary? What does the Test Industry Truly Need? --> Real Issues and Available Solutions

Organizer/Moderator:
Anis UZZAMAN (Cadence Design Systems, Inc. - USA)

9:00-10:20 Session 6B: DFT

A Scalable Scan Architecture for Godson-3 Multicore Microprocessor
Zichu Qi, Hui LIU, Xiangku LI, Da WANG, Yinhe HAN, Huawei LI, Weiwu HU (Chinese Academy of Sciences - China)

Kiss the Scan Goodbye: A Non-Scan Architecture for High Coverage, Low Test Data Volume and Low Test Application Time
Michael HSIAO, Mainak BANGA (Virginia Tech - USA)

Multiple Scan Trees Synthesis for Test Time/Data and Routing Length Reduction under Output Constraint
Katherine Shu-Min LI, Yu-Chen HUNG, Jr-Yang HUANG (National Sun Yat-Sen University - Taiwan)

Leveraging Partially Enhanced Scan for Improved Observability in Delay Fault Testing
Deepak K.G., Robinson REYNA, Virendra SINGH, Adit SINGH (Indian Institute of Science - India)

9:00-10:20 Session 6C: RF and Analog Testing

BIST Driven Power Conscious Post-Manufacture Tuning of Wireless Transceiver Systems Using Hardware-Iterated Gradient Search
Vishwanath NATARAJAN, Shyam Kumar DEVARAKOND, Shreyas SEN, Abhijit CHATTERJEE (Georgia Institute of Technology - USA)

Self-Calibrating Embedded RF Down-Conversion Mixers
Abhilash GOYAL, Madhavan SWAMINATHAN, Abhijit CHATTERJEE (Georgia Institute of Technology - USA)

A BIST Solution for the Functional Characterization of RF Systems Based on Envelope Response Analysis
Manuel J. BARRAGAN, Rafaella FIORELLI, Diego VAZQUEZ, Adoracion RUEDA, Jose L. HUERTAS (Universidad de Sevilla - Spain)

Exploiting zero-crossing for the analysis of FM modulated analog/RF signals using digital ATE
Nicolas POUS (LIRMM & Verigy - France), Florence AZAIS, Laurent LATORRE, Pascal NOUET (LIRMM - France), Jochen RIVOIR (Verigy - Germany)

10:40-12:00 Session 7A: SoC Test

IEEE 1500 Compatible Interconnect Test with Maximal Test Concurrency
Katherine Shu-Min LI, Yi-Yu LIAO, Yuo-Wen LIU, Jr-Yang HUANG (National Sun Yat-Sen University - Taiwan)

Multiple-Core under Test Architecture for HOY Wireless Testing Platform
Sung-Yu CHEN, Ying-Yen CHEN, Jing-Jia LIOU (National Tsing Hua University - Taiwan)

Partition Based SoC Test Scheduling with Thermal and Power Constraints under Deep Submicron technologies
Chunhua YAO, Kewal K. SALUJA, Parameswaran RAMANATHAN (University of Wisconsin-Madison - USA)

Test Integration for SOC Supporting Very Low-Cost Testers
Chun-Chuan CHI, Chih-Yen LO, Te-Wen KO, Cheng-Wen WU (National Tsing Hua University - Taiwan)

10:40-12:00 Session 7B: Test Generation (II)

Why is Conventional ATPG Not Sufficient for Advanced Low Power Designs?
Krishna CHAKRAVADHANULA, Vivek CHICKERMANE, Brion KELLER, Patrick GALLAGHER, Anis UZZAMAN (Cadence Design Systems - USA)

New Class of Tests for Open Faults with Considering Adjacent Lines
Hiroshi TAKAHASHI, Yoshinobu HIGAMI, Yuzo TAKAMATSU (Ehime University - Japan), Koji YAMAZAKI, Toshiyuki TSUTSUMI (Meiji University - Japan), Hiroyuki YOTSUYANAGI, Masaki HASHIZUME (The University of Tokushima - Japan)

Test Pattern Selection and Customization Targeting Reduced Dynamic and Leakage Power Consumption
Subhadip KUNDU, Krishna Kumar S., Santanu CHATTOPADHYAY (Indian Institute of Technology Kharagpur - India)

Deterministic Algorithms for ATPG under Leakage Constraints
Goerschwin FEY (University of Bremen - Germany)

10:40-12:00 Session 7C: Test Data Compression

Extended Selective Encoding of Scan Slices for Reducing Test Data and Test Power
Jun LIU, Yinhe HAN, Xiaowei LI (Chinese Academy of Sciences - China)

A Multi-Dimensional Pattern Run-Length Method for Test Data Compression
Lung-Jen LEE, Wang-Dauh TSENG, Rung-Bin LIN, Chi-Wei YU

Bit-Operation-Based Seed Augmentation for LFSR Reseeding with High Defect Coverage
Hongxia FANG, Krishnendu CHAKRABARTY (Duke University - USA), Rubin PAREKHJI (Texas Instruments - India)

Nov. 26, 2009

9:00-10:20 Session 8A: Panel Session (II):
Testing Embedded Memories in the Nano-Era: Will the existing approaches survive?

Organizer/Moderator:
Said HAMDIOUI (Delft University of Technology - Netherlands)

9:00-10:20 Session 8B: Fault Modeling & Diagnosis

A Non-intrusive and Accurate Inspection Method for Segment Delay Variabilities
Ying-Yen CHEN, Jing-Jia LIOU (National Tsing Hua University - Taiwan)

Bridging Fault Diagnosis to Identify the Layer of Systematic Defects
Po-Juei CHEN, James Chien-Mo LI (National Taiwan University - Taiwan), Hsing Jasmine CHAO (Taipei Medical University - Taiwan)

Delay Fault Diagnosis in Sequential Circuits
Youssef BENABBOUD, Alberto BOSIO, Luigi DILILLO, Patrick GIRARD, Serge PRAVOSSOUDOVITCH, Arnaud VIRAZEL (LIRMM - France), Olivia RIEWER

A Partially-Exhaustive Gate Transition Fault Model
Brion KELLER, Dale MEEHL, Anis UZZAMAN (Cadence Design Systems - USA), Richard BILLINGS (AMD - USA)

9:00-10:20 Session 8C: Analog and Mixed-signal Testing

An On-Chip Integrator Leakage Characterization Technique and Its Application to Switched Capacitor Circuits Testing
Chen-Yuan YANG, Xuan-Lun HUANG, Jiun Lang HUANG (National Taiwan University - Taiwan)

LFSR-based Performance Characterization of Nonlinear Analog and Mixed-Signal Circuits
Joonsung PARK, Jaeyong CHUNG, Jacob ABRAHAM (The University of Texas at Austin - USA)

A Jitter Characterizing BIST with Pulse-Amplifying Technique
An-Sheng CHAO, Soon-Jyh CHANG (National Cheng Kung University - Taiwan)

A Low-Cost Output Response Analyzer for the Built-in-Self-Test Sigma-Delta Modulator Based on the Controlled Sine Wave Fitting Method
Shao-Feng HUNG, Hao-Chiao HONG, Sheng-Chuan LIANG (National Chiao Tung University - Taiwan)

10:40-12:00 Session 9A: Memory Test

New Developments and Insights in Memory Test Algorithms
A.J. VAN DE GOOR (ComTex - Netherlands), Said HAMDIOUI, Georgi GAYDADJIEV, Zaid AL-ARS (Delft University of Technology - Netherlands)

Testability Exploration of 3-D RAMs and CAMs
Yu-Jen HUANG, Jin-Fu LI (National Central University - Taiwan)

Fault Diagnosis Using Test Primitives in Random Access Memories
Zaid AL-ARS, Said HAMDIOUI (Delft University of Technology - Netherlands)

10:40-12:00 Session 9B: Test Generation (III)

Test Generation for Designs with On-Chip Clock Generators
Xijiang LIN, Mark KASSAB (Mentor Graphics Corp. - USA)

On the Generation of Functional Test Programs for the Cache Replacement Logic
Wilson PEREZ (Universidad del Valle, Universidad Pedagógicay Tecnológica de Colombia - Colombia), Danilo RAVOTTO, Edgar Ernesto Sanchez SANCHEZ, Matteo SONZA REORDA, Alberto TONDA (Politecnico di Torino - Italy)

Compact Test Generation for Small-Delay Defects Using Testable-Path Information
Dong XIANG, Boxue YIN (Tsinghua University - China), Krishnendu CHAKRABARTY (Duke University - USA)

At-Speed Scan Test Method for the Timing Optimization and Calibration
Kun-Han TSAI, Ruifeng GUO, Wu-Tung CHENG (Mentor Graphics Corp. - USA)

10:40-12:00 Session 9C: Defect-Based Testing

M-IVC: Using Multiple Input Vectors to Minimize Aging-induced Delay
Song JIN, Yinhe HAN, Lei ZHANG, Huawei LI, Xiaowei LI, Guihai YAN (Chinese Academy of Sciences - China)

Analysis of Resistive Bridging Defects in a Synchronizer
Hyoung-Kook KIM, Wen Ben JONE (University of Cincinnati - USA), Laung-Terng WANG, Shianling WU (SynTest Technologies - USA)

On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification
Po-Yuan CHEN, Cheng-Wen WU (National Tsing Hua University - Taiwan), Ding-Ming KWAI (Industrial Technology Research Institute - Taiwan)

Test Pattern Selection for Potentially Harmful Open Defects in Power Distribution Networks
Yubin ZHANG, Lin HUANG, Feng YUAN, Qiang XU (The Chinese University of Hong Kong - Hong Kong)