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Keynote Speech

Keynote Speech 1 (Nov. 24th, 9:20-9:55)
Testing Challenges for Emerging Nanotechnologies

Presenter: Niraj K. JHA (Princeton University, USA)

The march to miniaturization of semiconductor technology continues. However, Moore’s Law does take a toll on Testing Engineers by making manufacturing-time testing ever more difficult. As if the testing challenges posed by the continued CMOS miniaturization were not enough, recognizing that CMOS is approaching its physical limits, new nanotechnologies are emerging with novel logic primitives that pose several new challenges in fault modeling, test generation, fault simulation, and design for testability.
This talk will begin with some of the testing challenges posed by current CMOS technology. Power-aware test has a rich history. However, we will show that temperature-aware test and power-aware test are not necessarily the same. Thus, a similar concerted effort is necessary for developing temperature-aware test techniques. Then we will move on to the test challenges posed by double-gate CMOS technology, such as FinFETs, which are expected to bridge the gap till the 10nm technology node as single-gate CMOS runs out of steam. Temperature-aware test will be even more important for FinFETs. Several nanotechnologies are vying to take us beyond the 10nm technology node, such as resonant tunneling diodes, quantum cellular automata, nanowires, nanotubes, graphene, single electron transistors, quantum computing, etc. We will finally discuss the testing challenges posed by some of these nanotechnologies.

Keynote Speech 2 (Nov. 24th, 9:55-10:30)
Wireless Testing and 3D Integrated Devices: Can They Save Our Jobs?

Presenter: Cheng-Wen WU (Industrial Technology Research Institute, Taiwan)

Testing has contributed a significant portion of the cost in manufacturing advanced semiconductor products. To address this issue, we have proposed the HOY test system, which features wireless communication and enhanced embedded test circuits. In this talk, we first provide the concept, architecture, and test flow for future semiconductor products tested by HOY. We then discuss in detail the testing of embedded memories and logic blocks by HOY. A prototype system has been developed and experimental results will be shown.
Another thought is about the development cost of a typical system-on-chip (SOC) using state-of-the-art technology---tens of million dollars for a case, and the cost continues to soar with the ever innovating technology. Today, more and more people are thinking about turning to three-dimensional (3D) integration for possible alternatives that provide better or equal performance with lower cost. Stacking dies using the Through-Silicon-Via (TSV) technology has been considered one of the most promising solutions to extending the life of Moore's Law in semiconductor industry, but of course there are problems to be solved before the infrastructure can be set up to support the industry for manufacturing TSV-based 3D integrated devices. In this talk we will also discuss the design and test issues, and possible solutions for 3D integrated devices. A link between HOY and 3D-IC testing will be established as well.

Keynote Speech 3 (Nov. 24th, 10:50-11:25)
Can innovations in Test serve as a beacon of light in a dark economy?

Presenter: Sanjiv Taneja, Cadence Design Systems, USA

While it is widely accepted that R&D innovations serve as the growth engine to gain market share and drive profitability in technology business, tough economic times present some big challenges to that premise. The first challenge is how to innovate when R&D budgets are tight and funding for new breakthrough ideas is limited. The second challenge -- specific to manufacturing test -- is that the true value of Test is cloaked under the myth of "high Cost of Test" leading some semiconductor businesses to stray away from adequate levels of investment that is needed to maintain the quality levels and withstand increasingly fierce competition in the era of economic globalization. Another challenge relates to linking innovation to business strategies when the short-term considerations become a barrier to moving the innovation process forward.

In this talk, we will address some of the solutions to these challenges by drawing upon real life experiences in the area of DFT/ATPG/Diagnostics in a corporate setting. The solutions range from managing innovation with a similar degree of discipline that gets applied to the rest of the business operations, creating an innovation-centric corporate environment, collaborating with customers and universities on high impact problems and creating the sparks of imagination that fuel the innovation process to focusing on rapidly transforming the innovations to complete solutions that meet customers' needs and maximize the return on investment.

Keynote Speech 4 (Nov. 24th, 11:25-12:00)
Challenges and Solutions for Testing TSV-Based 3D-SICs

Presenter: Erik Jan MARINISSEN (IMEC, Belgium)

Three-dimensional stacked ICs (3D-SICs) offer dense integration of possibly heterogeneous technologies at a small footprint. Interconnection of the various tiers by means of Through-Silicon Vias (TSVs) promises to increase the interconnect bandwidth and performance while lowering power dissipation and manufacturing cost, and hence might help the semiconductor industry to extend the momentum of Moore’s Law into the next decade.

Testing for manufacturing defects is considered by many as a major, still largely unresolved obstacle to make 3D integrated circuits a reality. It is regarded as the “No. 1 Challenge” among all challenges for 3D-SICs (Keynote Speech at the 2007 3D Architecture Conference by Ted Vucurevich, former CTO of Cadence Design Systems). There are concerns about testing cost, and even the feasibility of testing such TSV-based 3D-SICs.

In this presentation, after a review of TSV-based technologies, we present a structured overview of the challenges in testing 3D-SICs, along with solutions as far as available today. Whereas these ‘super chips’ require most of today’s advanced test and DfT approaches, they also have some unique challenges of their own. These include (1) development of new fault models and corresponding tests for thinned-die defects and TSV-based interconnects, (2) wafer probing on small and numerous micro-bumps and/or TSV tips under stringent damage requirements, (3) handling of and probing on wafers with thinned-die stacks, (4) further strengthening of the well-known modular test concept, (5) the design, partitioning, and optimization of DfT architectures that span across multiple dies, and (6) optimization of the test flow for maximum effectiveness and lowest cost.