Journal Papers
  • S.-J. Wang and M.D. Horng, “State assignment of finite state machines for low power applications,” Electronics Letters, Vol. 32, No. 25, pp. 2323-2324, 1996. (SCI) [83級 洪明德]
  • S.-J. Wang and C.-C. Lien, “Testability improvement by branch point control for conditional statements with multiple branches,” Journal of Information Science and Engineering, Vol. 16, No. 5, pp. 719-731, 2000. (SCI) [86級 連家駿]
  • M.-C. Wen, S.-J. Wang, and Y.-N. Lin, “Low-power parallel multiplier with column bypassing,” Electronic Letters, Vol. 41, No. 10, pp. 581-583, 2005. (SCI) [91級 溫明振]
  • N.-C. Lai and S.-J. Wang, “Low power BIST with smoother and scan-chain reorder under optimal cluster size,” IEEE Trans. on Computer-Aided Design, Vol. 25, No. 11, pp.2586-2594, Nov. 2006. (SCI) [91級 賴南成]
  • B.-J. Tsai, S.-J. Wang, C.-H. Lin, and T.-H. Yeh, “Test data compression for minimum test application time,” Journal of Information Science and Engineering, Vol. 23, No. 6, pp. 1901-1909, Nov. 2007. (SCI) [89級 蔡柏樟]
  • B.-J. Tsai and S.-J. Wang, “Multi-Mode Segmented Scan Architecture with Layout-Aware Scan Chain Routing for Test Data and Test Time Reduction,” IET Computer & Digital Techniques, Vol. 2, No. 6, pp. 434–444, 2008. (SCI) [89級 蔡柏樟]
  • S.-J. Wang, K.-L. Peng, K.-C. Hsiao, and K. S.-M. Li, “Layout-Aware Scan Chain Reorder for Launch-off-Shift Transition Test Coverage,” ACM Trans. Design Automation of Electronic Systems, Vol. 13, No. 4, Sep. 2008. (SCI) [93級 彭國霖]
  • S.-J. Wang, P.-C. Tsai, H.-M. Weng, and K. S.-M. Li, “Test Data and Test Time Reduction for LOS Transition Test in Multi-Mode Segmented Scan Architecture,” Int’l J. Electrical Engineer, Special Issue of VLSI/CAD, Vol. 15, No. 2, pp. 71-78, Apr. 2008. (EI) [89級 蔡柏樟]
  • S.-J. Wang, K. S.-M. Li, S.-C. Chen, H.-Y. Shiu, and Y.-L. Chu, “Scan-Chain Partition for High Test-Data Compressibility and Low Shift Power under Routing Constraint,” IEEE Trans. on Computer-Aided Design, Vol. 28, No. 5, pp. 716-727, May 2009. (SCI) [94級 陳世政]
  • S.-J. Wang and T.-H. Yeh, “High Level Test Synthesis with Hierarchical Test Generation for Delay Fault Testability,” IEEE Trans. on Computer-Aided Design, Vol. 28, No. 10, pp. 1583-1596, Oct. 2009. (SCI) [93級 葉東樺]
  • T.-H. Yeh and S.-J. Wang, "Power-Aware High-Level Synthesis with Clock Skew Management", IEEE Transaction on Very Large Scale Integration Systems (TVLSI), 2010 (to be appeared) [93級 葉東樺]

 

Conference Papers
  • C.-C. Wang and S.-J. Wang, “A new expander design for a wideband switching system,” in Proc. Workshop on Computer Applications, pp. 154-159, 1993. [81級 王啟信]
  • C.-C. Wang and S.-J. Wang, “Reducing test cost of sequential machines with lower hardware overhead,” in Proc. Workshop on Computer Applications, pp. 22-27, 1995. [81級 王啟信]
  • P.C. Hsu and S.-J. Wang, “Testing and diagnosis of board interconnects in microprocessor-based systems,” in Proc. 5th Asian Test Symp., pp.56-61, Hsinchu, Taiwan, 1996. [83級 許博清]
  • S.-J. Wang and M.-D. Horng, “State assignment for lower power consumption in sequential circuitst,” in Proc. Int’l Conf. on Computer Architecture (ICS’96), pp. 210-217, Kaohsiung, Taiwan, 1996. [83級 洪明德]
  • S.-J. Wang and T.-M. Tsai, “Tset and diagnosis of faulty logic blocks in FPGAs,” in Proc. Int’l Conf. on Computer-Aided Design, pp.722-727, San Jose, CA, USA, 1997. [84級 蔡志銘]
  • S.-J. Wang, J.-F. Yu, and C.-H. Ko, “Testing interconnect faults in core-based systems,” in Proc. 8th VLSI/CAD Symp., pp.47-50, Nanto, Taiwan, 1997. [84級 于傑芳]
  • S.-J. Wang and C.-N. Huang, “Testing and diagnosis of interconnect structures in FPGAs,” in Proc. 7th Asian Test Symposium, pp 283-287, Singapore, Nov. 1998. [85級 黃照能]
  • C.-Z. Yung and S.-J. Wang, “Behavioral synthesis-for-testability for conditional statements with multiple branches,” in Proc. Workshop on Computer Architecture, ICS’98, pp. 15-21, Tainan, Taiwan, Dec. 1998. [85級 楊中仁]
  • W. Lin and S.-J. Wang, “NSC98 Bus Interface Unit,” 微處理機研討會論文集, pp. 55-60, Hsinchu, Taiwan, May 1999.
  • S.-J. Wang and C.-J. Wei, “Efficient built-in self-test algorithm for memory,” in Proc. Asian Test Symposium, Taipei, Taiwan, Dec. 2000. [86級 魏震榮]
  • S.-J. Wang and S.-N. Chiou, “Generating efficient tests for continuous scan,” in Proc. Design Automation Conf., pp. 162-165, Las Vegas, Nevada, USA, June 2001. [87級 邱升南]
  • P.-C. Tsai and S.-J. Wang, “An FSM-based programmable memory BIST architecture,” in Proc. 2nd Workshop on Register Transfer Level Automatic Test Pattern Generation & Design for Testability (WRTL’01), pp. 97-104, Nara, Japan, Nov. 2001. [89級 蔡柏樟]
  • S.-J. Wang and Y.-H. Lin, “An adjustable BIST TPG design for low-power testing,” in Proc. 12th  VLSI/CAD Symp., 2001. [88級 林燕宏]
  • Y.-L. Hsu and S.-J. Wang, “Retiming-based logic synthesis for low-power,” in Proc. Int’l Symp. Low Power Electronics and Devices (ISLPED), pp. 275-278, Montery, CA USA., 2002. [88級 徐玉龍]
  • N.-C. Lai and S.-J. Wang, “A Reseeding Technique for LFSR-Based BIST Applications,” in Proc. 11th Asian Test Symposium, pp. 200-204, Nov. 2002. [91級 賴南成]
  • C.-F. Huang and S.-J. Wang, “Design of Low-Cost Self-Checking Circuits,” in Proc. Int’l Computer Symp., Dec. 2002. [89級 黃建峰]
  • P.-C. Tsai and S.-J. Wang, “Test Pattern Reordering for Low-Power Testing,” in Proc. VLSI/CAD Symp., Aug. 2002.  [89級 蔡柏樟]
  • P.-C. Tsai and S.-J. Wang, “Test Generation and Compaction for Continuous Scan,” in Proc. VLSI/CAD Symp., Aug. 2003.  [89級 蔡柏樟]
  • N.-C. Lai and S.-J. Wang, “Low Power BIST with Smoother,” in Proc. 13th Asian Test Symposium, pp. 40-45, Kenting, Taiwan, Nov. 2004. [91級 賴南成]
  • N.-C. Lai and S.-J. Wang, “Low Power BIST with Smoother,” in Proc. VLSI/CAD Symp., Aug. 2004. [91級 賴南成]
  • Y.-H. Fu and S.-J. Wang, “Test Data Compression with LFSR-Reseeding and Seed Overlapping,” in Proc. VLSI/CAD Symp., Aug. 2004. [91級 傅煜烜]
  • P.-C. Tsai and S.-J. Wang, “Test Data Compression for Minimum Test Application Time,” in Proc. VLSI/CAD Symp., Aug. 2004. [89級 蔡柏樟]
  • P.-C. Tsai, S.-J. Wang, and F.-M. Chang, “FSM-Based Programmable Memory BIST with Macro Command,” in Proc. IEEE Int’l Workshop on Memory Technology, Design, and Testing (MTDT), pp. 72-77, Taipei, Taiwan, 2005. [89級 蔡柏樟]
  • M.-C. Wen; S.-J. Wang, and Y.-N. Lin, “Low Power Parallel Multiplier with Column Bypassing,” in Proc. IEEE Int’l Symp. on Circuits and Systems, Vol. 2, pp. 1638-1641, Kobe, Japan, 2005. [91級 溫明振]
  • Y.-H. Fu and S.-J. Wang, “Test Data Compression with Partial LFSR-Reseeding,” in Proc. Asian Test Symp., Kolkata, India, Dec. 2005. [91級 傅煜烜]
  • F.-M. Chang and S.-J. Wang, “Interconnect-Aware High-Level Synthesis and Floorplaning,” in Proc. VLSI/CAD Symp., Aug. 2005.
  • T.-H. Yeh and S.-J. Wang, “Simultaneously Reducing Average Power and Peak Power in Behavioral Synthesis with Effective Shared Operations,” in Proc. VLSI/CAD Symp., Aug. 2005. [93級 葉東樺]
  • S.-J. Wang, K.-L. Peng, and K. S.-M. Li, “Layout-Aware Scan Chain Reorder for Skewed-Load Transition Test Coverage,” in Proc. Asian Test Symp., Fukuoka, Japan, pp. 169-174, Nov. 2006. [93級 彭國霖]
  • B.-J. Tsai and S.-J. Wang, “Multi-Mode Segmented Scan Architecture with Layout-Aware Scan Chain Routing for Test Data and Test Time Reduction,” in Proc. Asian Test Symp., Fukuoka, Japan, pp. 225-230, Nov. 2006.
  • S.-J. Wang and T.-H. Yeh, “High-Level Test Synthesis for Delay Fault Testability,” in Proc. Design, Automation, and Test in Europe, Nice, France, 2007. [93級 葉東樺]
  • S.-J. Wang, Y.T. Chen, and K. S.-M. Li, “Low Capture Power Test Generation for Launch-off-Capture Transition Test Based on Don’t-Care Filling,” in Proc. Int’l Symp. on Circuit and System, New Orleans, USA, pp. 27-30, May 2007. [93級 陳彥廷]
  • N.-C. Lai and S.-J. Wang, “Low-Capture-Power Test Generation by Specifying Minimum Set of Controlling Inputs,” in Proc. Asian Test Symp., pp. 413-418, Oct. 2007. [91級 賴南成]
  • S.-J. Wang, X.-L. Li, and K. S.-M. Li, “Layout-Aware Multi-Layer Multi-Level Scan Tree Synthesis,” in Proc. Asian Test Symp., pp. 129-132, Oct. 2007. [93級 李信龍]
  • S.-J. Wang, P.-C. Tsai, H.-M. Weng, and K. S.-M. Li, “Test Data and Test Time Reduction for LOS Transition Test in Multi-Mode Segmented Scan Architecture,” in Proc. Asian Test Symp., pp. 95-98, Oct. 2007. [89級 蔡柏樟]
  • S.-J. Wang, S.-C. Chen, and K. S.-M. Li, “Design and Analysis of Skewed-Distribution Scan Chain Partition for Improved Test Data Compression,” in Proc. Int’l Symp. on Circuit and System, Seattle, USA, pp. 2641-2644, May 2008. [94級 陳世政]
  • N.-C. Lai and S.-J. Wang, “On-Chip Test Generation Mechanism for Scan-Based Two-Pattern Tests,” in Proc. Asian Test Symp., Sapporo, Japan, pp. 251-256, Nov. 2008. [91級 賴南成]
  • S.-J. Wang, S.-J. Huang, and K. S.-M. Li, “Static and Dynamic Test Power Reduction in Scan-Based Testing,” in Proc. Int’l Symp. on VLSI Design, Automation, and Test, Apr. 2009. [95級 黃順傑]
  • K. S.-M. Li, M.-H. Hsieh, and S.-J. Wang, “Level Converting Scan Flip-Flops,” in Proc. Int’l Symp. on Circuit and System, June 2009. [95級 許槐煙]
  • S.-J. Wang, K.-L. Fu, and K. S.-M. Li, “Low Peak Power ATPG and Test Compactionfor n-Detection Test,” in Proc. Int’l Symp. on Circuit and System, June 2009. [95級 傅國霖]
  • C.-C. Wang, J.-W. Liu, R.-C. Kuo, K. S.-M. Li, and S.-J. Wang, “A 1.8 V to 3.3 V Level-Converting Flip-Flop Design for Multiple Power Supply Systems,” in Proc. Int’l Symp. Integrated Circuits, Singapore, Dec. 2009. [81級 王啟信]
  • T.-H. Tzeng and S.-J. Wang, “Fast and Accurate Statistical Static Timing Analysis,” in Proc. VLSI/CAD Symp., Hualian, Aug. 2009. [96級曾琮暉]
  • T.-H. Yeh and S.-J Wang "Thermal Safe High Level Test Synthesis for Hierarchical Testability", in Proc. Asain Test Symp., Dec., 2010. [93級 葉東樺]
  • T.-H. Yeh, S.-J Wang, and K. S.-M. Li "Interconnect Test for Core-based Designs with Known Circuit Characteristics and Test Patterns", in Proc. Int’l Conf. IC Design & Technology, Taichung, May 2011. [93級 葉東樺]

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